1. Field of the Invention
The present invention relates to a method for manufacturing semiconductor devices. More specifically, the present invention relates to a method for forming interlayer dielectric layers for interconnecting metal wiring layers.
2. Description of the Related Art
Generally, metallization wiring technology is crucial in IC (Integrated Circuit) devices for providing interconnections among transistors, paths for power supply and signal transmission.
Recently, the increase in integration demands of semiconductor devices has caused the decrease of wiring width, which in turn has led to narrower distances between the metal lines and increase in metal line height. Therefore, a gap filling process of the metal lines becomes important.
Conventionally, BPSG (BoroPhospho-Silicate Glass) film has been used because of its desirable gap filling properties. However, the BPSG film creates a high temperature process problem, and thus silicon dioxide (SiO2) films by CVD (Chemical Vapor Deposition) using HDP (High Density Plasma) are widely used.
FIG. 1 is a cross sectional view of a conventional semiconductor device.
Referring to FIG. 1, a lower insulating layer 11 is formed on a semiconductor substrate 10 and wiring layer 100 is formed on the lower insulating layer 11. The wiring layer 100 is comprised of a first Ti/TiN layer 12, metal layer of aluminum 13 and a second Ti/TiN layer 14 acting as ARC (Anti-Reflective Coating) film, all of them being sequentially stacked.
An inter-metal dielectric layer 15 made of SiO2 is formed by HDP-CVD to fill the gaps between the wiring layer 100.
A signal propagation speed is determined by parasitic capacitance (C) and resistance (R) between the wirings 100. Signal delay (T) can be represented by the following Equation 1:T∝RC  [Equation 1]
When the distance (d) between the wirings 100 decreases to less than 0.2 um as a result of higher integration demands, the parasitic capacitance between the wirings 100 tends to increase as seen from Equation 2:C=ε(S/d) (where, ε is dielectric constant, S is area of the wiring, and d is distance between wirings)  [Equation 2]
Therefore, in order to decrease the parasitic capacitance (C), the area (S) and dielectric constant (ε) should be lowered.
However, the inter-metal dielectric 15 is made of SiO2 having relatively high dielectric constant (ε) of 3.7˜4 and it is difficult to increase the area (S) because of the resistance (R) of the wiring 100. Therefore, the signal delay (T) according the higher integration is inevitable and thus it is difficult to realize modem semiconductor devices with small wiring sizing that can also achieve high speed signal transfer.